Issues regarding READ stability and stability in the half-select condition are limiting further scaling of conventional six-transistor (6T) static random access memory (SRAM) cells and circuits. Indeed, due to increased process variations including random mismatch, the READ and half-select stabilities are significantly lower in present and predicted future technologies, as compared to past technologies. Improvement of stability without significant area and/or power penalty is desirable.
Representative prior-art approaches are those set forth in Wang et al., “Single-Ended SRAM with High Test Coverage and Short Test Time,” IEEE Journal of Solid-State Circuits, v. 35 n. 1, January 2000, and in US Patent Application Publication 2005/0226084 of Hong entitled “Dual Port SRAM Cell.” FIG. 1 shows a typical prior-art single-ended eight-transistor (8T) SRAM cell 100. The cell 100 is interconnected with READ and WRITE word lines RWL, WWL, numbered 102, 104, a READ bit line RBLb, numbered 106, true and complementary WRITE bit lines WBL, WBLb, numbered 108, 136, a supply voltage VDD, numbered 110, and a ground 112. The ground can be broadly understood to encompass terminals maintained at a relative ground and not necessarily at zero electrical potential. The cell 100 includes a first inverter formed by transistors PL, NL, numbered 114, 116, and a second inverter formed by transistors PR, NR, numbered 118, 120, cross-coupled to the first inverter to form a storage flip-flop having first and second terminals 122, 124 and a flip-flop supply voltage terminal configured for interconnection with the first supply voltage VDD, numbered 110. Cell 100 also includes a left-hand WRITE access device SL, numbered 126, and configured to selectively interconnect the first terminal 122 to the WRITE bit line 108 under control of the WRITE word line 104.
Cell 100 further includes a pair of series READ access devices N1, N2, numbered 128, 130, configured to ground the READ bit line 106 when the READ word line 102 is active and the second terminal 124 is at a high logical level. Also included is a right-hand WRITE access device SR, numbered 132, which selectively connects second terminal 124 to complementary WRITE bit line 136 under control of WRITE word line 104. All the transistors are n-type field effect transistors (NFETS) except for PL and PR, which are p-type field effect transistors (PFETS). Prior art cell 100 is stable during a READ operation, as the node voltage is not disturbed. However, it has a larger area than the conventional 6T SRAM cell, due to the extra two NFETS N1, N2, and the additional bit line RBLb and word line RWL.
Accordingly, it would be desirable to further improve upon prior art techniques.